The JM800QSU-2G

• Is a 256M x 64bits DDR2-800 SO-DIMM. The JM800QSU-2G consists of 16pcs 128Mx8bits DDR2 SDRAMs in FBGA packages and a 2048 bits serial EEPROM on a 200-pin printed circuit board. The JM800QSU-2G is a Dual In-Line Memory Module and is intended for mounting into 200-pin edge connector sockets.
• Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Features

• RoHS compliant products.
• JEDEC standard 1.8V ± 0.1V Power supply
• VDDQ=1.8V ± 0.1V
• Max clock Freq: 400MHZ; 800Mb/s/Pin.
• Posted /CAS
• Programmable CAS Latency: 4, 5, 6
• Programmable Additive Latency :0, 1, 2, 3, 4, 5
• Write Latency (WL) = Read Latency (RL)-1
• Burst Length: 4, 8(Interleave/nibble sequential)
• Programmable sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver (OCD) Impedance Adjustment
• MRS cycle with address key programs.
• On Die Termination

Average Refresh Period:

• 7.8us at lower then TCASE 85°C
• Serial presence detect with EEPROM