DESCRIPTION:

• This document describes Kingston's 128M x 64-bit 1GB (1024MB) DDR2-800 CL5 SDRAM (Synchronous DRAM) memory module, based on sixteen 64M x 8-bit DDR2 FBGA components.
• This module has been tested to run at DDR2 800MHz at low latency timing of 5-5-5-15 at 2.0V.
• The SPD is programmed to JEDEC standard latency 667Mhz timing of 5-5-5-15 at 1.8V.
• This 240-pinDIMM uses gold contact fingers and requires +1.8V.

FEATURES:

• Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 5 (clock)
• Burst Length: 4, 8 (Interleave/nibble sequential)
• Programmable Burst type (sequential & interleave)
• Timing Reference: 5-5-5-15 at +1.8V / 5-5-5-15 at +2.0V
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
• Serial presence detect with EEPROM
• High Performance Heat Spreader
• PCB : Height 1.180” (30.00mm), double sided component